default_kernel_cost.bend
1# One clock assumption, 2.5 GHz (0.4 ns per cycle), prices both vector MACs
2# and scalar operations. A 4x8 step issues four 256-bit multiplies and four
3# adds for 32 MACs; with multiplies and adds on separate ports that is
4# conservatively four cycles. Scalar operations counted from source are
5# charged one cycle each: pool maxima and elementwise loops carry dependency
6# chains, so the core's issue width is not assumed.
7# Copy cost rounds the retained 0.090833 ns/byte upper quartile upward.
8# See docs/design.md for instruction sources, assumptions and residuals.
9import Base
10import stelliferous@0.0.2.0/kernel_cost.bend as Cost
11
12def cycle_ns() -> F32:
13 0.4
14
15def configuration() -> Cost.Configuration:
16 # Prior task traces measured 40--180 us per wake round. Two rounds are
17 # charged explicitly: the 250 us leaf grain alone cannot cover both maxima.
18 Cost.Configuration{(4.0 / 32.0 * cycle_ns() : F32),0.100,cycle_ns(),250000.0,180000.0}